AMS Verification Engineer

Swedium the growing is Global System Engineering and Solution Company, offers services like Engineering R & D Services, Embedded Systems, custom application development, Onsite Consultancy and Testing Services to clients across the globe for onsite and offshore business model. We provide industry solutions to our customer through our dedicated development center in Bangalore (India) and Stockholm (Sweden).


We are looking for AMS Verification Engineer
You will
Responsible for verification of a design, being block or sub-system
Define and implement UVM based test environments
Create Verification Specifications and defining test cases
Develop, run and debug test cases
Continuously improve and optimize ways of working
Generate documentation
Secure design quality
Develop competence in technical domain


To be successful in the role you must have
A MSc degree in a technical field or the equivalent level of education
Several years’ experience from verification using System Verilog and UVM.
Experience in developing verification test plans and directed/randomized test cases
Experience in Mixed Signal Verification
Good communication in English
The ability to be agile and meet expectations


We also want you to have experience
From Formal Verification
Using real-numbered analog behavioral models in SystemVerilog/Verilog-AMS or electrical behavioral models in Verilog-A
With signal processing using Matlab
In Gate-level Netlist simulations
In Agile way of working



Kindly share your Cv at pratik.pandey@swediumglobal.com


www.swediumglobal.com