Analog Layout Engineer

Xenergic AB is a high-tech semiconductor company providing cutting edge high-speed, low-power embedded memory solutions in advanced technology nodes. These memories are targeted for market segment ranging from IoT and mobile applications to high-end servers. We are looking for a very passionate layout design engineer.


The key skills required for the position are as follows:
M.SC. in electronics engineering or related fields
At least 3 years job experience in analog SoC layout design
Experience in sub-28nm technology nodes
Fluent in English both in writing and speaking
Good communication skills and ability to work in a team
Ability to drive complex tasks autonomously



The following competences are not mandatory but would be beneficial:
Understanding of memory design and system level integration
Experience with chip level DRC/LVS
EMIR-aware layout design concepts
Understanding of the impact of layout on post-layout parasitics
Scripting skills (python, bash, csh); SKILL is a big plus



We are looking for a highly motivated and talented physical design engineer to join our team to work on the next generation of memory solutions. The key responsibilities in this position include design of leaf cells under tight area and integration constraints, porting of physical designs between technologies, optimization of blocks for EMIR mitigation, test chip design finishing on the DRC/LVS level, PAD integration etc. The position will require tight collaboration with other team members from layout, analog, digital and coding teams.