Application Engineer

Senior Principal Application Engineer (R35740)
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
This Digital IC design and support role offers an opportunity to work on a variety of digital implementation and support activities associated with Cadence EDA tools for Synthesis, Logical Equivalency Checking (LEC), Design-for-Test (DFT) and Static Timing Analysis (STA).
You may get involved in design services projects and/or supporting customers using Cadence tools on their projects in areas such as 5G, IOT, automotive, advanced CPU, wireless, audio, image processing, AI, machine learning etc.
Following are the key job responsibilities:
Be the primary focal point for technical issues, questions, and discussions for a given customer engagement
Lead technical discussions with customers and is the primary technical interface between customer and Cadence R&D. Capable of influencing outcomes among customers, R&D and Cadence technical team members.
Develop an understanding of the customer's needs and also of the
competition's technology and sales strategies.
Perform methodology assessments, improve existing design methodologies, and develop new ones that leverage Cadence technology and services.
Create and conduct technical presentations and product demonstrations to customers
Helps mentor other AEs
Good consulting/client skills. Deliver results with minimal day-to-day guidance
Review, document and resolve project technical issues. Escalation of issues to Project Management when appropriate



The ideal candidate should have:
Solid understanding of ASIC Design implementation process and steps
Exposure and experience with Synthesis tools (Genus, RTL Compiler or Design Compiler)
Strong hands-on experience with DFT tools (Modus, DFTCompiler, LogicVision)
Strong hands-on experience running Logic and Low Power Equivalency tools, ability to debug and isolate issues
Ability to understand and write RTL (System Verilog, Verilog, VHDL)
Debug and resolve complicated PPA, Low Power implementation and TAT issues related to DFT flows
Be able to provide actionable feedback to downstream flows as well as derive actionable items to tune synthesis flow to improve metrics
Exceptional troubleshooting and analytical skills


Requirements:
MS in EE with minimum 10+ years industry related experience in design and/or EDA (Digital Front End Implementation)
5+ Years of experience in Cadence Front-End Digital Implementation tools including Genus, Modus, Conformal
5+ Years of DFT experience and expertise in DFT Architecture, DFT insertion, Pattern Generation, Hierarchical Test and Low Power / Power aware ATPG
3+ Years of STA experience and expertise Advanced Node timing closure
Excellent command in scripting languages such as Perl, Tcl and shell scripting essentials
Strong problem solving & analysis skills covering digital implementation
Proven track record and experience working in a fast-paced environment
Excellent customer interaction & presentation skills



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