Application Engineer - Digital IC Design

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
Principal Application Engineer
This Digital IC design and support role offers an opportunity to work on a variety of digital implementation and support activities associated with Cadence EDA tools for Synthesis, Logical Equivalency Checking (LEC), Design-for-Test (DFT), Place & Route and Static Timing Analysis (STA).
You may get involved in design services projects and/or supporting customers using Cadence tools on their projects in areas such as 5G, IOT, automotive, advanced CPU, wireless, audio, image processing, AI, machine learning etc.
This role is ideal for someone with several years of hands on ASIC/IC design experience who is looking for a new challenge in an absorbing customer facing role.
This role requires strong technical capability in Cadence tools, flow development, and the ability to think outside of the box.
Job responsibilities:
Support customers using Cadence EDA software in one or more of these areas:
Synthesis, DFT, Logical Equivalency Checking
Low Power Design Implementation, SDC Verification
Place and Route
Parasitic Extraction, Timing Signoff, Power Signoff
Be the primary focal point for technical issues, questions, and discussions for a given customer engagement
Lead technical discussions with customers and is the primary technical interface between customer and Cadence R&D. Capable of influencing outcomes among customers, R&D and Cadence technical team members.
Develop an understanding of the customer's needs and also of the competition's technology and sales strategies.
Perform methodology assessments, improve existing design methodologies, and develop new ones that leverage Cadence technology and services.
Create and conduct technical presentations and product demonstrations to customers
Helps mentor other AEs
Good consulting/client skills. Deliver results with minimal day-to-day guidance
Review, document and resolve project technical issues. Escalation of issues to Project Management when appropriate



Requirements:
MS in Electronics Engineering with minimum 10+ years industry related experience in design and/or EDA,
5+ years of experience in Synthesis (Genus or Design Compiler), DFT (Modus, DFTCompiler, LogicVision) and Logic Equivalency tools
Or Cadence or other place and route tools (Physical Synthesis, PnR, CTS, Static Timing Analysis)
Debug and resolve complicated PPA, Low Power implementation and TAT issues.
Exceptional troubleshooting and analytical skills
Excellent command in scripting languages such as Perl, Tcl and shell scripting essentials
Strong problem solving & analysis skills covering digital implementation
Proven track record and experience working in a fast-paced environment
Excellent customer interaction & presentation skills



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