Application Engineer – Functional Verification

In this pivotal role you will be a front-line contact with Cadence customer’s engineers and CAD teams and will have 2 main responsibilities:


o  Provide technical customer support for Cadence Functional Verification products, remotely, via email and telephone as well as on-site;


o  Take part in technical campaigns to enable our customers to adopt existing and new technologies and solutions.


You will develop expertise in functional verification across multiple products within the Cadence Functional Verification Suite. We are looking for you to work independently and also in collaboration with other team members to resolve customer issues, support technology adoption and identify opportunities and risks associated with those activities.


In this varied role, you will also work closely with the R&D and Marketing organisations to communicate customer requirements, influence product direction and validate solutions.


Of course, you will work closely with the Sales team to support technical sales campaigns and this will give you the opportunity to develop the skills needed to demonstrate and adapt solutions to meet customer requirements.


Lastly, we envisage that you will develop the ability to deliver training courses and workshops covering the Functional Verification Platforms and over time mature into a strong team member and become a key contributor, leading projects and initiatives.


The position will include travel to customer sites and involve significant interaction with customers.


We are looking for strong candidates with:


o  BEng in Electronic / Micro-Electronic Engineering or Computer Science – or equivalent


o  Experience of Hardware Design and Verification languages including Verilog, VHDL, System Verilog, System-C, TLM.


o  Experience with Unix / Linux environment including scripting languages.


o  Good Communication skills: speak and write English to a high level and have strong skills within an international environment.


For your future colleagues we are looking for team oriented people, paralleled with an ability to work independently and bring new initiatives. Of advantage would be:


o  Experience of Verification environments such as UVM, SystemVerilog, SystemC, Specman/e, Metric/Coverage driven verification and Formal property checking.