Applications Engineer

We are seeking a verification Applications Engineer (AE) to drive the adoption and expansion of the Synopsys verification solution in Scandinavia.

Candidates should have an in-depth knowledge of Constrained Random Verification methodologies and hands-on experience in SV/UVM-based environments.

Experience with VHDL, SystemC and TLM would be an advantage, as would experience with static and formal verification tools. In this role, you will work directly with customers to assist with the deployment of Synopsys verification tools and methodologies, resolve technical issues and provide technical training. Our ideal candidate is motivated, autonomous and a good communicator.

Key Qualifications:
BS in CS/EE with 7+ years of experience, or MS in CS/EE with 5 years of experience.
Strong knowledge of System Verilog/UVM, Verilog, SystemC and VHDL is required.
Minimum 3+ years of experience with Block Level and SOC Level simulation verification is required.
Knowledge of Constrained Random Verification and Code/Functional/Assertions(SVA) Coverage closure.
Sharp debugging skills on designs and System Verilog/UVM environments is needed.
Experience with static checking tools such as SpyGlass.
Critical thinking and problem-solving skills are a plus.
Pleasant personality with good customer interface and communication skills.



Preferred Experience:
Knowledge of low power verification.
Knowledge of TLM design and verification.
Knowledge of protocols such as JESD, AMBA, ENET and PCIE.