ASIC Designer

ASIC Designer Location: Stockholm, Sweden Xelerated develops and markets IC devices and related SW products for the high end Network Processor market.Job Description Xelerated develops and markets IC devices and related SW products for the high end Network Processor market.The development of IC devices is fully undertaken within our teams in Stockholm and Tel Aviv.These teams manage all aspects of development of very large integrated circuits, i.e.architectural design, VHDL design, verification, layout, technology and IP selection.Xelerated is a company in fast expansion and in order to meet demands for future generations of network processing technology, we are now actively recruiting engineers with limited professional experience.The right candidate is a talented and ambitious individual with the objective to be part of a world class ASIC team that consistently is exposed to the most demanding design challenges.As an ASIC Designer at Xelerated, you will be responsible for the implementation of hardware architectures in VHDL.It is expected that you jointly with systems architects and senior designers, defines and independently implements solutions to proposed architectures.The designer will over time be able to assume functional responsibility at a high level of abstraction, delivering VHDL implementations that meet functional requirements, as well as area and timing constraints posed by the technology.The designer also participates in verification during certain phases of a project.Xelerated offers a challenging environment where architects, designers, verification engineers and layout engineers work closely to meet the market requirements of next generation products.The two design sites, Stockholm and Tel Aviv, are fully integrated into the same project.You will report to the[Vice President and Head of ASIC & HW Development.Specific tasks will Include VHDL design of complex hardware architectures Use of internal and external IP in VHDL and Verilog RTL verification on block level and subsystem level Design of test benches for use by designers and verification engineers Use of a variety of EDA tools for design and verification Candidate Profile MScEE or equivalent is required 2-3 years of professional experience of ASIC or FPGA design Advanced usage of VHDL and related simulators is required Experience from verification tools and methodologies is a benefit Located in the Stockholm area or willing to relocate