OBS! Ansökningsperioden för denna annonsen har
passerat.
Arbetsbeskrivning
PrimeComp is a engineering consulting company with assignments in energy, industry and infrastructure. Through our combined experience and unique range of technology areas, we offer services to create profitable, innovative and sustainable solutions.
Work Description:
We are looking for an experienced ASIC designer. Our world leading customer within the telecom area is looking for an experienced ASIC designer (3+ years of relevant experience).
The purpose of the role is to develop modules in the customers next generation of ASICs for Radio equipment and Radio Access Network compute. The modules performs advanced signal processing. This role includes:
- Systematization
- RTL development
- Verification and product documentation.
Competence Profile:
- Master of Science in Electrical Engineering, Computer Engineering or equivalent education.
- Looking for a person that have several years of experience in ASIC design using SystemVerilog.
- Have experience in working with micro-architecture/systematization.
- Proficiency in English (speaking and writing).
Competences:
SystemVerilog, RTL design, Processor architecture, Signal processing, Synthesis.
Useful competences:
Scripting and Matlab.
Personality:
- Appreciation for continuous improvement and optimized ways of working.
- Leadership skills.
- An outstanding interest in learning new things every day and want to make a difference.
- A very positive attitude and thrive new challenges.
- Problem solving skills (and the flair to use them creatively - where there is change, you see opportunities).
- Team spirit, be a very communicative person, but also work well independently.
- Result oriented attitude, keeping high quality and acting on time.