ASIC FPGA VERIFICATION DESIGN ENGINEER

Swedium the growing is Global System Engineering and Solution Company, offers services like Engineering R &amp D Services, Embedded Systems, custom application development, Onsite Consultancy and Testing Services to clients across the globe for onsite and offshore business model. We provide industry solutions to our customer through our dedicated development center in Bangalore (India) and Stockholm (Sweden).


We are looking for ASIC Verification Engineer


Requirements:


Minimum 6-8 years' experience
 Excellent skills in SystemVerilog/UVM
 Good programming skills (neat, commented, maintainable code, no warnings). Quality
Conscious!
 Excellent debugging skills with complex designs
 Experience with IP level and system level verification
 Proficient in verification planning, reporting and driving verification closure. Must understand
how a verification project works, from start to finish
 Must be able to work both in team and independently
 Good communication skills, both written and oral English

Good to have:
 Experience with Matlab, and signal processing is meritorious
 Experience with analog-mixed signal type ASICs is meritorious
 Experience using formal properties and tools, such as Jasper, OneSpin, InFact and similar
 Experience in using golden models/reference models in a test bench
 C-programming and/or scripting skills
 Interest in verification methodology, quality and driving improvements
 Experience in agile ways of working, in particular agile scrum


Kindly share your Cv at pratik.pandey@swediumglobal.com


www.swediumglobal.com