ASIC Verification Engineer

Several years of working experience in ASIC or FPGA verification and simulation on IP, sub-system and/or chip level using SystemVerilog UVM
Experience defining and implementing UVM test environments including coverage closure
Knowledge of C/C++
Knowledge of Embedded Software design and test
Experience working with Multi Core Architecture
Experience of TCL/Python/Perl/etc…
Experience from verification in lab
Appreciation for continuous improvement and optimized ways of working
Leadership skills
Proficiency in English, speaking and writing
Master of Science in Electrical Engineering, Computer Engineering or equivalent education.
An outstanding interest in learning new things every day and wish to make a difference
A very positive and ready to challenges attitude
Great cooperation and communication skills
Readiness to work well independently and make sure to reach results with high quality and on time