ASIC Verification Engineer

Having 10+ Years of experience in ASIC Design Verification.
Experience in hardware verification language System Verilog, Verilog and VHDL.
Strong Experience in methodologies like UVM/OVM.
Experience in Formal Verification using Jasper Gold.
Experience in System level verification using C/C++.
Experience in both SoC and IP based verification.
Experience in Leading Team and Planning.
Good understanding of RTL to GDS flow.
Expertise in writing Test cases and Developing Verification Environment.
Experience on coverage driven random and assertion-based verification.
Have Knowledge & Experience in AMBA APB & AXI protocols.
Confident, flexible, hands on, able to work well in the fast-paced environment.


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