ASIC Verification Engineer – 2886 - Stockholm

Veritaz is a leading IT staffing solutions provider in Sweden, committed to advancing individual careers and aiding employers in securing the perfect talent fit. With a proven track record of successful partnerships with top companies, we have rapidly grown our presence in the USA, Europe, and Sweden as a dependable and trusted resource within the IT industry.
Assignment Description:
We are looking for a Senior ASIC Verification Engineer to join our dynamic team.
What you will work on:
Contribute to new and existing ASIC projects, participating in IP design/verification and various levels of SubSys integration/verification.
Collaborate within teams, either at modern headquarters in Solna – Stockholm or at customer offices in the Stockholm area.
Engage in a mix of IP design/verification and different levels of SubSys integration/verification.

What you bring:
Broad experience in ASIC verification, with a preference for a minimum of one year working with UVM.
Proficient in UVM verification and SystemVerilog.
Background in working with complex ASIC and/or large FPGA design.
Previous experience in IP block verification.
Familiarity with multi-clock domains.
Competence in RTL within Verilog, VHDL, and/or SystemVerilog.
Strong English skills, both spoken and written

Meritorious:
Expertise in test bench structuring and design.
Demonstrated leadership qualities.
Knowledge of RTL design.
Proficiency in scripting.
Lab experience.
Background in telecommunications.