OBS! Ansökningsperioden för denna annonsen har
passerat.
Arbetsbeskrivning
Responsibilities
You will be responsible for SoC/ASIC architecture design for 5G wireless products, to define requirement specification, evaluate IPs, define hardware blocks, create simulation environment, run simulation, drive technical studies, and coordinate works between different teams. You are going to work closely with physical layer algorithm developers, hardware designers and embedded SW experts. The project is organized in very close cooperation with the Huawei wireless teams in Shanghai.
Qualifications and experience
To be successful in this role the candidate should have more than 5+ years industrial or academia experience in areas of SoC, such as processors, interconnect, interfaces, scheduling, cache/DMA, memory system, power consumption and design methodology. You should have knowledge in embedded SW, and hands-on skills in block design with Verilog/VHDL. C++ or systemC experience is strongly required.
Knowledge in wireless physical layer application is preferred.
A Master Degree or Ph.D in electrical engineering, computer architecture, or equivalent background is required.
Other
The candidates should have highly developed skills in finding new innovative solutions, strategic visions and ability of leading and driving activities. Prior experience from international and multicultural work is preferred. As we are a global company the candidate must be able to communicate fluently in English, both verbally and in writing.
Location
This is a position at our R&D office in Kista, Stockholm, Sweden. Business travel is expected, both within Europe and to China.