Digital ASIC Packaging Engineer

Do you want to work with advanced ASIC development in the forefront of technology? Are you ready to join a team responsible for the very heart of the Axis products - the ARTPEC SoC chip - where your contribution really matters and where team collaboration is the way to success? We are now looking for ASIC Package Engineer to further strengthen our ASIC System team in Lund.

Who is your future team?
The ASIC System team plays an important role in the development of next generations of ARTPEC SoC chips. The team takes an active part in both previous and ongoing ASIC projects as well as monitoring of design flows and technology trends that are crucial for future generations of ARTPEC SoC chips.

Learn more; https://newsroom.axis.com/article/artpec-foundation-quality

The ASIC System team consists of Project Managers, System Architects, and Implementation Engineers. The Implementation team handles Power, Synthesis, STA, Package and much more. Our team is responsible for the overall specification as well as the execution of the ASIC projects. We work in close collaboration with our ASIC vendor, our internal RTL design and verification teams as well as key internal stakeholders to specify and implement the required functionality of the SoC design.

We are a highly skilled and motivated team with a mix of both junior and senior team members. Our strength lies not only in the individual competence of each team member but also in the open working environment and strong collaboration within our team. We are now looking for an ASIC Implementation Engineer to strengthen our team with an ASIC Implementation Engineer with focus on Synthesis/STA.

What you will do as ASIC Package Engineer
The Co-design between the PCB and the ASIC becomes an increasingly important task with the smaller transistor dimensions in the newer technologies. In addition, we also see increases in the speed and bandwidth requirements for many external interfaces. If an ASIC is designed without considering the system impact, it may have significant negative impact on performance.

You will strengthen our ASIC team and bring focus within the area of packaging, including power and signal integrity, to meet the challenges we face going forward.

You will bring knowledge and knowhow about evaluating novel package options, 2.5D and 3D stacking, and package-on-package, as well as tasks in bump-map and ball-map specification and optimization, on die and in package, to meet the SI and PI requirements put on the system.

You will understand how different low power design techniques impact the power integrity of the system. It is helpful to understand low power architecture when looking at the package design. It is beneficial to understand and work with power specifications, including power domains with multi-voltage and DVFS requirements.

You will know the importance about external interfaces that also impact the package design. High-speed interfaces, including DRAM and PCIe, need special consideration. Other interfaces also impact. It is valuable to understand them, and their electrical properties and specifications.

Who are we looking for/Who are you?
You are an analytic and dedicated team player with a strong personal drive and an ability to work both unsupervised and as a part of a team. You enjoy working with package and PI/SI but can also participate in strategy and architectural discussions as well as understand power related topics such as UPF and have a great understanding of RTL code.

You have an ability to create and maintain the needed network for your task including internal stakeholders and external partners.

We'd love to hear that you have/are:

* MSc level in Electrical Engineering, Computer Science, or other equivalent education.
* At least 6 years of work experience.
* Significant experience in internal package
* 2.5D/3D stacking technologies
* Experience in bump map optimization.
* Experience in ball map specification.
* Experience in Power Integrity/Signal Integrity analysis
* High Speed interface knowledge
* Knowledge in floor planning and physical implementation.
* Knowledge in scripting languages (Python, Perl, TCL, Linux Shell scripting etc.)
* Experience in tools such as GiT and Jira
* Communication and presentation skills in English.
* Quality-consciousness.
* Travels may be needed but not required on a frequent basis.

The position is office-based, and you will be located at Axis HQ in Lund, Sweden.

What Axis have to offer?
Openness might be a buzz word in other companies, but at Axis this is the core of who we are. Our most important asset is our ability to cooperate. We have realized that great ideas can come from anywhere. This is why we encourage everybody to contribute and innovate. If you are a person that likes to get involved and make a difference and nudge the world a little bit in the right direction, you will find a home with us.

We want you to enjoy working with us! Therefore, we offer great benefits, e.g., flexible working hours, classic Swedish fika on Fridays, breakfast every day, corporate bonus, physical training grants, insurances, your very own Axis bicycle, and relocation assistance if needed - just to name a few.

Curious to discover more?
We have a host of places where you can learn more about Axis; our products and solutions, our company culture, and what working at Axis is really like. Check out:

Life at Axis blog
Engineering at Axis blog
Innovation at Axis

Ready to Act?
Do you want to join us? Apply today! Contact our recruiting ASIC Systems Manager Tomas Larsson at phone +46 46 272 1500 if you want more information.