Digital ASIC Verification Engineer

Acconeer is a start-up company recently listed on Nasdaq First North developing a low power 60 GHz/mmWave radar sensor – a pulsed coherent radar based on research from Lund University. It combines extremely low power consumption and sub-mm distance detection accuracy. Further, the radar sensor provides detection of micro-motions, velocity estimation, material classification, human breathing rate and much more, all within a sensor sized 5x5 mm including antennas.

Acconeer is located in Lund at Ideon Gateway and we are currently a group of around 30 people with high R&D focus, working closely together over the different R&D disciplines - hardware, software and algorithm research. · Experience working with state of the art ASIC verification methods (e.g. constrained random, functional coverage, formal methods, etc.)
· Skilled in ASIC verification tools as: Questa, Incisive or similar
· Skilled in the following languages: SystemVerilog, UVM, C, Phyton, SystemC/TLM, SciPy/NumPy
· Experience working with embedded micro controllers
· Experience working with mixed analog/digital verification
· A science/engineering Master’s degree
· English language skills
· Ability to prioritise tasks effectively and focus
· Possess the drive to succeed combined with a ‘make it happen’ attitude
· Comfortable working in a fast moving and dynamic start-up environment - Be responsible for the verification of the digital parts of our next generation sensor chip
Define the verification methodology for the different development phases
Develop and maintain the verification environment
Run the verification on RTL and netlist and report coverage
- Define verification friendly system and implementation together with architects and design team
- Define low level SW drivers to be reused by the SW developers together with SW and design team