FPGA Designer for high-speed communications: Telecom

We are looking for an experienced FPGA designer, with a passion for backend design, to one of our team working towards the telecom industry. The teams work mainly derives of tasks like Block or Top Level Floor planning, Bus/Pin Planning, Clock Tree Synthesis, Placement, Optimization, Routing, Static Timing Analysis. But there might also be task that requires knowledge in lab environment. The team way of working is agile and high collaboration skills are needed to be able to work with other team members and teams.

Key competences:

- VHDL/Verilog programming experience
- Experience with Xilinx and/or Altera platform and tools (Quartus or ISE etc.)
- Experience in Xilinx/Altera backend flow
- Floor planning
- Vivado tool
- Timing analysis
- Experience in multigigabit transceivers
- Scripting (TCL, Python, Perl)
- Worked with tools as: - Spyglass - Cadence - ClearCase
- English only is sufficient language skill for this assignment


Additional information

- Team works mostly remotely but occasional travel to the office in Solna will occur
- CET Office hours
- Remote from Sweden is possible