FPGA/ASIC Top Level Verification engineer

Requirements
• Experience in FPGA and/or ASIC Top-Level Verification
• Excellent skills in SystemVerilog
• God skills in C-programming
• Experience in UVM
• Excellent skills in several standard interfaces, such as Ethernet, I3C, SPI, SGMII, CPRI etc
• Excellent skills in AMBA design, AXI, AHB, APB
• Excellent debugging skills with complex designs
• Must be able to work both in a team and independently
• Good communication skills, both written and spoken English
• Good skills in working with UNIX and/or Linux
• Ability to travel to Kista, Stockholm every two months
• At least 7 years in ASIC/FPGA industry


Following experience will be a beneficial asset
• Experience with analog-mixed-signal type ASICs
• Good understanding of ASIC and FPGA design and verification flow
• Experience in LAB, using Lauterbach, signal generators etc
• Experience in Netlist simulation
• Experience using formal properties and tools, such as Jasper or similar
• Experience in agile ways of working
• Clearcase version control system experience
• VHDL knowledge
• Scripting in Perl, Python, Bash or C-shell