Sr Principal Application Engineer

Job Description: AE5 Verification Engineer

Cadence Design Systems is looking for a candidate to be part of its verification application engineering team . If you like to architect and develop solutions for challenging problems in a fast and innovative paced environment, using state of the art technology this is a great opportunity.

This position is located in Lund or Kista, Sweden

Job Description:
As an integral member of the verification application engineering team, you will work with industry leading semiconductor and system companies to deploy Cadence’s market leading simulation Verification products. You will work with the EMEA based AE and sales teams to provide technical support in the Pre and Post-Sales process.
In this pivotal role the you will be a front-line contact with Cadence customer’s engineers and CAD teams and will the following responsibilities:

Providing technical support for the deployment of Cadence’s market leading simulation Verification products;
Working with the various Cadence sales teams and product developers to develop innovative solutions to address customer’s challenging problems;
Providing proactive support and problem consultation to make our product users successful;
Collaborating with R&D to introduce new verification flows and Apps to customers;
Championing customer needs and helping R&D to develop competitive and creative technical solutions;
Understanding the competitive landscape and continuously working on differentiating Cadence’s solutions;
Fostering a collaborative, team-oriented, work environment;
Representing Cadence at technical conferences and trade shows;
Applying Cadence verification products to diverse functional verification problems.
Deliver training course for formal verification technology
Technical leader on projects and initiatives.

The position will include travel to customer sites and involve significant interaction with customers.
We are looking for strong candidates with:
BEng in Electronic / Micro-Electronic Engineering or Computer Science – or equivalent
Experience in using Cadence verification products like Xcelium and vManager
Experience of Hardware Design and Verification languages including PSL, SV Verilog, VHDL, System Verilog, System-C, TLM.
Experience of the IP/ Soc verification process
Experience with Unix / Linux environment including scripting languages.
Good Communication skills
Speak and write English to a high level and have strong skills within an international environment.