Verification Engineer (Formality tool)

Swedium Global is the growing System Engineering and Solution Company, offers services like Engineering R&D and Services to clients across the globe for onsite and offshore business model. We provide industry solutions to our customer through our dedicated development center in Bangalore (India) and Stockholm (Sweden).


www.swediumglobal.com


We are looking for Design Verification Engineer with Formality Tool Experience
Total Experience:5+ Years
BE/BTech/ME/MTech with E&C.
Proven expertise in logic equivalent checking gates-to-gates, gates to power-aware gates using Formality.
Knowledge of Verilog/VHDL.
Expert in logic equivalence checks using LEC RTL to Netlist, Netlist to Netlist.
Expert in low power checks Good understanding of UPF.
Expert in Synthesis with Synopsys tools Design Compiler and Design Compiler Topographical.
Perl and TCL/TK required to achieve highly automated, reproducible and fast results.


Please send your Cv at pratik.pandey@swediumglobal.com