Verifier to ASIC team

Would you like to participate in exciting cutting-edge projects?

In that case, we have the right position for you! We are currently forming a new team and expanding existing teams to contribute to bringing bright ideas and complex designs to life. Therefore we are looking for skilled ASIC-verification engineers to join us and be part of successful a group. You will be involved in new and existing ASIC projects working in teams. The work can be carried out either at AFRY’s modern and airy head office in Solna - Stockholm or at our customer's offices in the Stockholm area.

Knowledge and experience:

- You have a solid background with more than 3+ years of experience in ASIC verification
- Good command of UVM verification and SystemVerilog
- Used to work with complex ASIC and/or large FPGA design
- Experience from IP block verification
- Multi clock domains
- RTL within Verilog, VHDL, and/or SystemVerilog
- Good English skills, in both speech and writing


Meritorious if you have:

- Test bench structuring and design
- Leadership qualities
- RTL design knowledge
- Scripting skills
- Lab experience
- Telecommunication


Response and Interviews will be starting at beginning of August

Keywords: ASIC, Verilog, FPGA, Developer, Embedded Systems, Consulting, Consultant, Design System Architect, Verification, lab, SystemVerilog, UVM

English only is sufficient language skill for this assignment